Field programmable gate arrays (FPGAs) typically have at least two distinct programmable features. One such feature is the logic block, which typically may be programmed to assume a variety of logic functions such as some or all Boolean logic functions for a given number of inputs. The other such feature is the interconnection of such logic blocks via paths that interconnect the outputs and inputs of several logic blocks in a selected sequence to achieve a desired result. Numerous programmable routing structures have been designed to achieve various levels of choice in routing signal paths through a programmable device. U.S. Reissue Pat. No. Re. 34,363, which is incorporated herein by reference and title to which is held by the assignee hereof, discloses a programmable routing structure in the first FPGA. U.S. application Ser. No. 08/761,113 now issued as U.S. Pat. No. 5,818,730, entitled "FPGA One Turn Routing Structure and Method Using Minimum Diffusion Area", which is referenced above and incorporated herein by reference, discloses a one-turn programmable routing structure with minimum diffusion area.
Prior art programmable routing structures typically consist of interconnect lines programmably connectable by a dispersed number of switching devices such as field effect transistors, the selected conditions of which (i.e., open or closed) determine the chosen path for a signal communicated between programmed logic blocks through such routing structures. A larger number of available paths through such a routing structure provides more flexible routing, but there is a penalty for the added flexibility. The dispersal of switching devices often requires numerous diffusion areas within the integrated circuit device, which use a large amount of silicon surface area. To minimize cost, surface area must be used efficiently, particularly where a relatively large number of signal paths must be provided within a relatively small surface area. The larger the number of available paths through a routing structure, i.e. the more flexible the routing structure and the more routable the paths through the structure, the less efficient the usage of surface area becomes. Therefore, there is a need to provide a flexible routing structure which nevertheless minimizes diffusion surface area.
Further, for signals on paths that turn within the programmable routing structure, many prior art structures connect a given interconnect line to a corresponding perpendicular interconnect line. For example, if a group of parallel interconnect lines is considered to consist of a group of adjacent "lanes", and there are corresponding lanes in the other three compass directions, an interconnect line in one group entering the structure in the first such lane will leave the structure in the same lane of a perpendicular group. Since connections to logic block inputs and outputs are often different for different lanes, it is desirable for a routing structure to permit lane-changing.
Yet further, for typical prior art programmable routing structures, each path through the structure has the same or approximately the same delay. However, paths traveling long distances within the FPGA have increased capacitive loading and increased resistance due to having several field effect transistors in series, and therefore are generally slower than paths traveling shorter distances. Such a long path can easily be implemented as a single long straight path, or as a path with only one turn. If such paths could be made faster relative to paths with more turns, a smaller delay would result for longer paths, which in turn would lead in some cases to a faster overall speed for the programmed circuit. Therefore, there is a need to provide a routing structure with a fast path for signals passing straight through the structure.